IC/analog layout with 2nm/3nm/5nm, high-speed layout
Technology
Job Description
Analog Layout Engineer
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Bay Area, CA
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Exp : Minimum 8 years and above
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Skill : 2nm, 3nm and 5nm process and high speed layout (MUST)
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Blocks : LDO ,ADC and SERDES
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Tools : Cadence ,Virtuoso XL