Design Engineer

Job Description

DPP is seeking a Senior Designer Engineer for an opportunity with our client in the Aerospace industry.

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Work Location: Fully remote but looking at Huntsville AL or El Segundo CA

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Duration: 8 months

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Terms: W2 Contract

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Responsibilities:

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• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).

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• Develop verification methodologies and test benches for block and system-level verification.

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• Create and execute test plans, develop test harnesses, and implement coverage models.

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• Conduct timing analysis, noise analysis, and other signoff checks.

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• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.

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• Support lab integration and troubleshooting activities.

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• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

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Required Qualifications:

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• 7+ years of experience in ASIC design and implementation.

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• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.

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• Experience with FPGA & ASIC design.

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• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).

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• Experience with Linux development environment.

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• Experience with design verification and test bench development.

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Preferred Qualifications:

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• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field.

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• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test).

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• Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs.

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• Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM).

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• Strong object-oriented programming and scripting skills (Python, TCL, Perl).

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• Experience with physical design flows and industry-standard EDA tools.

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• Experience with RTL2GDSII physical design and signoff flows.

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• Knowledge of deep sub-micron FinFET and CMOS technologies.

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• Experience with DFT/Scan/MBIST/LBIST methodologies.

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• Experience mentoring junior engineers.

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