ASIC/SoC Verification Architect

Job Description

Job Description

• Key Requirements:
  10 years of experience in ASIC/SoC verification and verification architecture.
  Strong hands-on SystemVerilog, UVM, Verilog, and constrained-random verification.
  Experience developing verification strategies, test plans, testbenches, coverage models, and verification environments.
  Strong knowledge of SoC architecture, RTL, CPU/processor, interconnects, memory, and IP verification.
  Experience with UVM/SystemVerilog assertions, functional/code coverage, simulation, and debugging.
  Familiarity with C/C , Python, scripting, formal verification, and emulation is a plus.
  Experience leading verification teams and working with design, architecture, firmware, and validation teams.
  
  Ideal Candidate: Someone who can own verification architecture from planning testbench design implementation coverage debug sign-off.