Solution Director- SOC & ASIC Design Services
Job Description
Scope & Responsibilities
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Our client, a leading global technology and engineering services organization, is seeking a senior technical leader to define and shape solution strategy across complex SoC and ASIC design engagements.
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This is a senior individual contributor role serving as a primary technical authority in pre-sales and solutioning environments. The leader will partner directly with semiconductor clients to shape pursuit strategy, lead technical discovery, architect solutions, and ensure proposals are grounded in credible engineering and delivery frameworks. This role does not carry a sales quota.
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Key Responsibilities
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- Lead technical solutioning for ASIC and SoC design pursuits, from initial discovery and scoping through proposal development and client presentations.
- Define engagement models and delivery architectures spanning RTL design, DFT, physical design, signoff, verification, and tape-out support.
- Develop differentiated technical solutions across synthesis, place-and-route, functional verification, formal verification, and low-power design.
- Engage directly with chip architects, design leaders, and engineering executives to understand technical requirements, program objectives, and tool environments.
- Develop reusable solution patterns and reference architectures based on successful client engagements.
- Contribute thought leadership around AI-assisted semiconductor design, advanced-node tape-out readiness, chiplets, and multi-die architectures.
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Key Selection Criteria
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Required
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- 15+ years of hands-on ASIC and/or SoC design experience, with deep expertise in at least two areas:
- RTL / microarchitecture
- Design for Test (DFT)
- Physical design
- Functional verification (UVM/SVA)
- Low-power design (CPF/UPF)
- Demonstrated experience in a pre-sales, solution architecture, consulting, or client-facing technical leadership role, ideally within an engineering services, semiconductor, or EDA environment.
- Strong command of major EDA ecosystems, including Synopsys, Cadence, and/or Siemens EDA.
- Experience with advanced semiconductor process nodes, ideally 7nm and below.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, VLSI Design, or a related technical discipline.
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Preferred
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- Experience with chiplet architectures, UCIe, and/or multi-die integration.
- Familiarity with AI/ML accelerator architectures, NPUs, and inference-engine design challenges.
- Experience translating highly complex semiconductor engineering requirements into client-facing solutions, architectures, and delivery models.
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Confidentiality
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This is a confidential executive search. Additional information regarding the organization, reporting structure, and broader mandate will be shared with qualified candidates during the search process.
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